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An 800 Mbps multi-channel CMOS serial link with 3× oversampling
S. Kim, K. Lee, D. Jeong, D.D. Lee, and A. Nowatzyk
Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, May, 1995, pp. 451 - 455.

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A CMOS serial link is described that uses a digital PLL with 3× over-sampling to recover both clock and data. An implementation with 0.6 ?m CMOS technology exhibits 800 Mbps operation with BER of less than 10E-12 for pseudo random number sequence. Chip area and power dissipation per channel at 800 Mbps are 2.1 mm×1.1 mm and 0.75 W, respectively

Number of pages: 5

S. Kim, K. Lee, D. Jeong, D.D. Lee, and A. Nowatzyk, "An 800 Mbps multi-channel CMOS serial link with 3× oversampling," Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, May, 1995, pp. 451 - 455.

@inproceedings{Kim_1995_4958,
   author = "Sungjoon Kim and Kyeongho Lee and Deog-Kyoon Jeong and D.D. Lee and Andreas Nowatzyk",
   title = "An 800 Mbps multi-channel CMOS serial link with 3× oversampling",
   booktitle = "Proceedings of the IEEE 1995 Custom Integrated Circuits Conference",
   month = "May",
   year = "1995",
   pages = "451 - 455"
}